Memory devices, such as dynamic random access memories (“DRAMs”), include one or more arrays of memory cells arranged in rows and columns. Each array may be divided into several sub-arrays. Typically, one or more digit or “bit” lines are provided for each column of the array, and each digit line is coupled to a respective sense amplifier. Each sense amplifier is generally a differential amplifier that compares the voltage at one of its inputs to the voltage at the other of its inputs. The sense amplifier then drives its inputs to complementary logic levels corresponding to the sensed differential voltage.
An array architecture that is commonly used in memory devices, such as DRAMs, is an “open digit line array” or “open array” architecture. In an open array architecture, a sense amplifier is coupled to the digit lines of two adjacent sub-arrays. Each of the digit lines is coupled to memory cells in the respective memory sub-array. Thus, each sense amplifier is shared by two sub-arrays so that one input to the sense amplifier is coupled to the digit line of one array and the other input to the sense amplifier is coupled to the digit line of the other array. Prior to a memory read operation, the digit lines are precharged to a voltage DVC/2 that is typically one-half a supply voltage.
During a read operation, a word line representing a row of memory cells is activated in the memory sub-array having the memory cell to be access. The activated word line coupled each memory cell of the row to a respective digit line. In response, the voltage on each digit line either increases or decreases from DVC/2 depending upon the logic level stored in the respective memory cell. The other digit line of each of the sense amplifiers remains at the precharge voltage DVC/2. Each sense amplifier detects that the voltage on the digit line coupled to the memory cell being accessed has either increased or decreased relative to the precharge voltage DVC/2 and then drives the respective digit lines to complimentary logic levels corresponding to the sensed voltage. The data latched by one of the sense amplifiers is then selected based on a column address for the desired memory cell.
In a modification to the sensing scheme previously described, the digit lines are precharged to ground rather than precharged to the DVC/2 voltage. The grounded digit line scheme is desirable for low voltage operating conditions because a DVC/2 voltage precharge is unsuitable with the threshold voltage of the sense amplifiers under the low voltage conditions. In low voltage conditions, the DVC/2 voltage is at a voltage level that barely switches on the transistors of the sense amplifiers, resulting in relatively slow sense times. The sensing operation for a grounded digit line scheme is similar to that for a DVC/2 precharge scheme, and has the advantage of being able to switch on p-channel transistors of the sense amplifiers quickly. Upon coupling a memory cell to one of the grounded digit lines, the other digit line of the sense amplifier is coupled to a reference voltage. Based on the voltage of the digit line coupled to the memory cell relative to the digit line coupled to the reference voltage, the sense amplifier drives the digit lines to complementary voltage levels and latches the data state of the memory cell. That is, the digit line coupled to the memory cell is driven to ground and the reference digit line is driven to a supply voltage by the sense amplifier in response to the digit line coupled to the memory cell having a lower voltage than the reference digit line. Conversely, the digit line coupled to the memory cell is driven to the supply voltage and the reference digit line is driven to ground by the sense amplifier in response to the digit line coupled to the memory cell having a higher voltage than the reference digit line.
A stable and reliable reference voltage is important for the functionality of a grounded digit line scheme. Variations in the reference voltage, in severe cases, can cause the sense amplifier to sense and latch incorrect data. For example, if the reference voltage shifts to a greater voltage due to process, voltage, or temperature (“PVT”) variations, a condition exists where the digit line coupled to a memory cell can be forced to ground, although the digit line should have been driven to the supply voltage. The voltage of the digit line coupled to the memory cell would have been otherwise greater than the reference voltage if not for the shift in the reference voltage to a higher voltage. As a result, the sense amplifier senses and latches an incorrect data state. In lower voltage operating conditions, stability and reliability of the reference voltage is even more critical because the same absolute shifts in the reference voltage represent greater relative shifts with lower operating voltages.
Most semiconductor memory devices will be subject to PVT variations during fabrication and operation. Thus, the memory devices must be designed with sufficient PVT margin to operate correctly under these conditions. However, as lower operating voltages are used, designing a sense amplifier and precharge scheme having sufficient margin for correct operation becomes increasingly difficult. Therefore, there is a need for an alternative sense amplifier and precharge scheme that can provide a stable and reliable reference voltage despite PVT variations.